CLKPHA=SAMPLELEADING, MASTER=SLAVE, CSINV=AL, CLKPOL=IDLELOW
No Description
| MASTER | Main mode 0 (SLAVE): Secondary mode 1 (MASTER): Main mode |
| CLKPOL | Clock Polarity 0 (IDLELOW): The bus clock used in synchronous mode has a low base value 1 (IDLEHIGH): The bus clock used in synchronous mode has a high base value |
| CLKPHA | Clock Edge for Setup/Sample 0 (SAMPLELEADING): Data is sampled on the leading edge and set-up on the trailing edge of the bus clock in synchronous mode 1 (SAMPLETRAILING): Data is set-up on the leading edge and sampled on the trailing edge of the bus clock in synchronous mode |
| CSINV | Chip Select Invert 0 (AL): Chip select is active low 1 (AH): Chip select is active high |
| AUTOTX | Always Transmit When RXFIFO Not Full |
| AUTOCS | Automatic Chip Select |
| CLKPRSEN | PRS CLK Enable |
| FORCELOAD | Force Load to Shift Register |
| SDIV | Sync Clock Div |